GODBRAIN // AVALON-PAUT
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GODBRAIN  ·  Technical Brief

AVALON⁠-⁠PAUT

A 64-channel phased-array ultrasonic instrument, built from the silicon up.

64 CH/ ±100 V/ FPGA beamforming/ on-device imaging/ REV 2026.07
01 System

One signal chain. Every stage in-house.

Excitation, receive, beamforming, and image reconstruction are all our own design — not a sealed OEM inspection board wrapped in a chassis.

Excite
HV Pulser
TX7332 · ±100V
Receive
Analog Front-End
AFE5832 · 32ch
Form
FPGA Beamformer
CrossLink-NX
Reconstruct
DSP · Imaging
FMC → TFM
Infer
Edge Inference
on-device
// owning the chain sets the cost floor, removes the import dependency, and puts inference on the instrument.
02 Baseline configuration

AVALON-PAUT / spec

Channels
64  2 × 32, individually wired
Pulser
TX7332 — ±100 V, on-die T/R switch
Receive AFE
AFE5832 — integrated LNA / VGA / ADC
Beamformer
Lattice CrossLink-NX (LIFCL-40)
Focusing
SPI-loaded delay profiles · coded-excitation roadmap
Imaging
Full-Matrix Capture → TFM
FE protection
on-die T/R + polymer ESD suppressor
Control
STM32 host + FPGA control plane
// Phase 1b brings up Zone 4 (pulser + AFE + ±100 V + transducer) standalone before the 24-layer integration spin.
03 Position

A closed, imported category — reopened at the silicon level

The incumbent shape
  • PAUT instruments ship as sealed OEM platforms — Olympus OmniScan, Eddyfi Gekko, Sonatest Veo.
  • List price $40–80k, imported, closed firmware, no edge intelligence.
  • Regional buyers carry the FX + import + service overhead on every unit.
Our position
  • We own pulser, AFE, beamformer, and imaging — a real cost floor, not a markup on someone else's board.
  • Sovereign supply — no Western platform dependency; dual-use adjacent.
  • On-device inference is native to the architecture, not bolted on.
04 Status

Where the design stands

  • ✓Entity incorporated — GODBRAIN A.Ş., active.
  • ✓Silicon access secured — TI NDA signed, register maps in hand.
  • ✓FPGA design complete — CrossLink-NX beamformer, first bitstream built.
  • ✓±100 V HV subsystem — designed & simulation-verified.
  • ✓Phase 0 control board — fabricated, in hand.
  • ✓IP in-house — schematic + FPGA RTL + DSP, no license fees.
The high-uncertainty work — architecture, silicon access, supply chain — is closed. What remains is layout, fab, and bench bring-up: execution, not discovery.
05 Supply & access

Register-level access to the critical silicon

Texas Instruments
TX7332 · AFE5832
HV pulser + analog front-end. Signed NDA grants register-level design access.
design-level silicon access
NDA signed
Würth Elektronik
±100 V HV magnetics
High-voltage flyback transformer. Engineering thread open, sample process active.
EFD-class · 12V → ±100V
Sampling
Lattice Semiconductor
CrossLink-NX · LIFCL-40
FPGA beamformer. Symbol, pinout, and RTL design complete; first bitstream built.
on-chip beamforming
Design done
// NDA-level silicon access is the gate that stalls most hardware efforts for years. For AVALON it is open.
06 Roadmap

Each milestone is a technical gate

2026 Q3
64-channel layout + fab-prep — FPGA control plane routed; design-complete.
2026 Q4
Validated prototype — first pulse → receive → image on a reference block.
2027 H1
First paid pilot inspections — production probe + calibration; measurable field reports.
2027 H2
AVALON X1 pre-commercial — certification path; first customers; Series-A readiness.
2028+
Platform scale — the same acquisition + inference core across adjacent domains.
07 Scope

The acquisition + inference core generalizes

AVALON is the first instrument. The same wave-physics acquisition and on-device inference core carries into adjacent inspection domains — one engineering base, several products.

Shipping first
AVALON-PAUT
Phased-array ultrasonic industrial inspection.
Energy
GODSUN
Solar / energy asset inspection & analytics.
Robotics
DroneOps / Crawler
Autonomous robotic inspection carriers.
Software
Cloud Twin
Digital-twin + asset-risk portal.
08 Raise

Seed — $150–250K

Target: a validated prototype and first paid pilots (the 2026-Q4 → 2027-H1 inflection). The first tranche (~$150K) reaches the working prototype.

The high-uncertainty spend is already behind us. This capital converts a proven design into working hardware and field data — execution, not de-risking.
Use of funds
PCB fab + BGA assembly$25–40K
Silicon + HV + parts (5–10 units)$15–25K
Probes (prototype + pilot)$8–15K
Lab / bench (scope, PSU, JTAG, reflow)$12–20K
Founder runway (12–18 mo)$50–80K
Certification start + buffer$20–30K
Seed total$150–250K

The hard parts are done.
The rest is execution.

Sovereign, silicon-level phased-array inspection. AVALON is the first instrument off a reusable acquisition + inference core.

GODBRAIN A.Ş. · godbrain.io · AVALON-PAUT · REV 2026.07